1. Field of the Invention
The present invention relates generally to a register apparatus and method. In particular, the present invention relates to an apparatus and method for reducing power consumption through effective gating in a register module of a user core.
2. Description of the Related Art
Due to the recent widespread use of mobile communication technology, increasing the operation time of a mobile station (MS) through effective use of its limited power resources has become a significant issue. To meet this demand, various low power designs have been used for recently developed chips.
Multi-function chips typically include a Central Processing Unit (CPU)/Digital Signaling Processor (DSP) and peripheral devices. Each device is connected to other devices by bus interfaces. Usually, the peripheral devices are provided with register modules for communicating with the CPU. The CPU controls the peripheral devices performing predetermined operations through the register modules. Therefore, almost every user core is provided with a register module.
The register module has a write functionality for writing a register value by the CPU and a read functionality for enabling the CPU to read a particular signal. Under some circumstances, the register module has read and write functionality that allows a value written by the write action to be read directly by the read action. Typically, the register module can comprise write registers, read registers, and read and write registers in combination.
In a design flow of the register module of the user core, the register module is first described in a Hardware Description Language (HDL) according to its various interfaces and then synthesized into gate-level logics by a synthesis tool. Thus, a designer designs the register module for the user core by the HDL according to the design flow. Interconnections between the gate-level logics in designing the register module depend on how the HDL is described.
There is a typical register module having gate level logics created to operate in a one-way gating fashion by the synthesis tool. The register module gates a write address at a write operation using a chip select (CS) signal that activates the register module, thereby performing a gating function as intended by the designer. This register module comprises a writer and a reader.
As previously described, the typical gate level structure is created by synthesizing what the designer describes in HDL using its own optimization function, or by providing a HDL description using an option of a synthesis tool in consideration of the gate level structure before synthesizing and then synthesizing the HDL description. These two structures can be created using general HDL technology. The configuration of a register module that can be formed by the general HDL technology will be described below.
FIG. 1 illustrates the configuration of a register module of a conventional one-way gating structure. Referring to FIG. 1, the operation of each block for read and write functionality when a CS signal is enabled for the register module will be described separately from its operation when the CS signal is disabled. Gating logics in the register module are implemented as AND gates.
A write operation when the CS signal, CS is enabled for the register module will now be described. At a write operation, a write enable signal, WRITE_enable is enabled.
When an input address signal, ADDR is enabled, a common address decoder 102 is activated. If both CS and WRITE_enable are enabled, that is, the output of an AND gate 100 is activated, the output of the common address decoder 102 activates a write address decoder 103 via a one-way gating logic 101. Thus, a load enable signal at an address corresponding to ADDR is enabled, thereby writing a value BUS_IN in a corresponding register of a write register 105.
Regarding the operation of a reader 110 during the write operation, when ADDR is enabled, the common address decoder 102 is activated. The output of the common address decoder 102 is provided directly to a read address decoder 104 without passing through a gating logic and activates logics of the read address decoder 104. If the read address decoder 104 uses an address corresponding to ADDR, corresponding AND gates in a read gating logic 106 are enabled. Therefore, in the case of a read and write address, read data is provided to a bus output multiplexer (MUX) 107 and activates the MUX 107.
A gating logic 108, which has been activated by CS, outputs a bus output signal BUS_OUT in response to the output of the bus output MUX 107. BUS_OUT is not used at the next stage (not shown) because the register module is currently in a write state. That is, many logics corresponding to the reader 110 operate unnecessarily during the write operation in the register module illustrated in FIG. 1.
A read operation when CS is enabled will now be described. At a read operation, WRITE_enable is disabled.
When ADDR is enabled, the common address decoder 102 is activated. The output of the common address decoder 102 is provided directly to the read address decoder 104 without passing through a gating logic and activates a corresponding AND gate in the read gating logic 106. In the case of a read and write address, read data is provided to the bus output MUX 107 and activates it.
The gating logic 108, which has been activated by CS, outputs BUS_OUT in response to the output of the bus output MUX 107. BUS_OUT is used as a at the next stage because the register module is currently in a read state.
Meanwhile, regarding the operation of a writer 109 during the read operation, when ADDR is enabled, the common address decoder 102 is activated. Although CS is enabled, WRITE_enable is not. Thus, neither the output of an AND gate 100 nor the one-way gating logic 101 is activated. That is, the common address decoder 102 is activated, but the read address decoder 103 is not. Thus, the one-way gating logic 101 activates none of the logics of the writer 109.
Finally, the operation of each block when CS is not enabled will now be described.
If another register module writes or reads, ADDR is enabled, activating the common address decoder 102. However, since CS is not enabled, the output of the AND gate 100 is not activated. Thus, the one-way gating logic 101 is not activated either and thus none of the logics of the writer 109 operate.
In the reader 110, when the common address decoder 102 is activated, the output of the common address decoder 102 is directly provided without passing though the gating logic and activates the logics of the read address decoder 104. Then, the read gating logic 106 is activated and in the case of a read and write address, read data is provided to the bus output MUX 107. While the bus output MUX 107 is activated by the output of the read gating logic 106, the gating logic 108 is not activated by CS. As a result, BUS_OUT is not output.
As described above, the logics before the gating logic 108 in the reader 110 operate using CS. The operation results in unwanted continuous power consumption which was not intended to occur by the designer.
FIG. 2 illustrates the configuration of another register module of the conventional one-way gating structure. Referring to FIG. 2, the operation of each block for read and write functionality when CS is enabled for the register module will be described separately from its operation when CS is disabled. Gating logics in the register module are implemented as AND gates.
A write operation when CS is enabled for the register module will now be described. At a write operation, WRITE_enable is enabled.
When ADDR is enabled, a gating logic 200 activates a common address decoder 202 using CS and ADDR. An AND gate 211 AND-operates CS and WRITE_enable. The outputs of the AND gate 211 and the common address decoder 202 activates a one-way gating logic 203, thereby activating a write address decoder 204. Thus, a load enable (LE) signal, at an address corresponding to ADDR is enabled, thereby writing a value BUS_IN in a corresponding register of a write register 206.
Regarding the operation of a reader 210 during the write operation, the output of the common address decoder 202 is provided directly to a read address decoder 205 without passing through a gating logic and activates the decoders logics. If the read address decoder 205 uses an address corresponding to ADDR, corresponding AND gates in a read gating logic 207 are enabled. Therefore, in the case of a read and write address, read data is provided to a bus output MUX 208.
The bus output MUX 208 outputs BUS_OUT in response to the output of the read gating logic 207. As stated earlier, BUS_OUT is not used as at the next stage (not shown) because the register module is currently in a write state. Also in the register module of FIG. 2, many logics corresponding to the reader 210 operate during the write operation.
A read operation when CS is enabled will now be described. At a read operation, WRITE_enable is disabled.
When ADDR is enabled, the gating logic 200 activates the common address decoder 202 using CS and ADDR. The output of the common address decoder 202 is provided directly to the read address decoder 205 without passing through the gating logic and activates corresponding decoding logics and then a corresponding AND gate of the read gating logic 207. In the case of a read and write address, read data is provided to the bus output MUX 208.
The bus output MUX 208 outputs BUS_OUT in response to the output of the read gating logic 206. BUS_OUT is used at the next stage because the register module is currently in a read state.
Meanwhile, regarding the operation of a writer 209 during the read operation, when ADDR is enabled, the common address decoder 202 is activated. But since WRITE_enable is not enabled, an AND gate 211 to which WRITE_enable is applied does not activate the one-way gating logic 203. Thus, the write address decoder 204 is not activated. As noted, the one-way gating logic 203 does not operate the logics of the writer 209 during the read operation.
Finally, the operation of each block when CS is not enabled will now be described.
Because the gating logic 200 is not activated, even if ADDR is enabled, neither the writer 209 nor the reader 210 is activated. The gating logic 201 is gated by a read signal 0, read-signal_0 corresponding to “address 0” from the previous stage of the reader 210, which detects the operation of the reader 210 when ADDR is gated and not activated by the gating logic 200 at the front end of the common address decoder 202 from its operation when ADDR is gated and activated by the gating logic 200. This gating logic 201 prevents unnecessary outputting of BUS_OUT, read-signal_0 when CS is not enabled. This is because when ADDR is gated by the gating logic 200, a load enable signal corresponding to “address 0” is generated.
Accordingly, the gating logics 200, 201 and 211 are not activated by CS so that neither writer 209 nor the reader 210 operates in the structure of FIG. 2. As compared to the register module of FIG. 1, the register module of FIG. 2 does not cause unnecessary power consumption when CS is not enabled.
Both the register modules as described above experience unnecessary power consumption as many logics corresponding to the reader operate when CS is enabled. Although the register module illustrated in FIG. 2 prevents unnecessary power consumption when CS is not enabled, it still experiences unnecessary power consumption during a write operation.
As described above, the conventional one-way gating technology operates many logics in a reader during a write operation or when CS is not enabled, thereby causing unnecessary power consumption.